(1) Field of the Invention
The invention generally relates to a method used in semiconductor manufacturing and, more particularly, to a serial to parallel data converter used in the fabrication of integrated circuits (ICs).
(2) Description of Prior Art
Serial to parallel data converters have numerous applications in electronics including circuitry where serial data from a disk or CDROM are converted to parallel format to be processed within a computer. As processing speeds increase and memory sizes grow, there is a need to reduce the time necessary to convert data from serial to parallel format.
Refer now to FIG. 1 showing a typical serial to parallel data converter. A plurality (n) of first D flip-flops (DFFA) 10-13 are provided. A serial data stream (DATA_IN) is applied to the input of each DFFA 10-13. A plurality (n) of phase clocks are applied to the corresponding clock input of each latch 10-13 such that CLK0 is applied to DFFA0, CLK1 is applied to DFFA1, etc. The output of each DFFA 10-13 is connected to the input of a corresponding second D flip-flop (DFFB) 15-18. CLKnxe2x88x921 is connect through a delay 19 to each clock inputs of DFFB 15-18. The outputs of each DFFB 15-18 correspond to parallel data PD0 through PDnxe2x88x921. The operation of the circuit of FIG. 1 is as follows. DATA_IN are applied to the plurality of DFFA (10-13). On the rising edge (for example) of each phase clock (CLK0-CLKnxe2x88x921) the corresponding serial data bit is stored on the output of its respective DFFA. Once all n data bits are stored, the clock inputs of each DFFB 15-18 are simultaneously triggered and the data are then transferred to the corresponding parallel data output PD0 through PDnxe2x88x921. The parallel data are then ready for use. The process is repeated and when the next n data bits are received, new parallel data appear at the output.
The problem with this circuit is that as speeds increase, the DFFs 15-18 may not be able to load properly before the next data bit is latched into DFFA0 10. Additionally, as serial data speeds increase, the processor using the parallel data may not be able to keep up with the presentation of parallel data. Thus, the serial data transfer must be stopped until the processor is ready to accept more parallel data. It is therefore necessary to find a better method to transfer serial to parallel data.
Other approaches related to improving serial to parallel data conversion circuits exist. U.S. Pat. No. 6,259,387 B1 to Fukazawa describes a serial-parallel converter, which uses a plurality of data extraction units, a delay unit and parallel registers for storing data for parallel distribution. U.S. Pat. No. 6,052,073 to Carr et al. discloses a serial-parallel converter using a shift register, a parallel latch and a controller for enabling and synchronizing the data stream. U.S. Pat. No. 5,777,567 to Murata et al. shows a serial-parallel converter using a delay line and phase locked loop (PLL) to synchronize the data. U.S. Pat. No. 5,561,423 to Morisaki describes a serial-parallel converter operating at high-speed and low power dissipation and utilizing differential flip-flops.
A principal object of the present invention is to provide a serial to parallel data conversion method utilizing a high-speed clock and high data rate application.
Another object of the present invention is to provide a serial to parallel data conversion circuit utilizing a high-speed clock and high data rate application.
A further object of the present invention is to provide a serial to parallel data conversion method that avoids the problem of setup between parallel loading of data and latching of the next serial data bit.
A still further object of the present invention is to provide a serial to parallel data conversion circuit that avoids the problem of setup between parallel loading of data and latching of the next serial data bit.
These objects are achieved using a serial to parallel data conversion method and circuit where the first serial data word is stored within a first n-bit register prior to presentation at the n-bit parallel output. The second serial data word is stored within a second n-bit register while the first serial data word stored within the first register is presented in parallel format at the output. The third serial data word is then stored within the first n-bit register while the second serial data word stored within the second register is presented at the output. Thus odd serial data words are stored within the first n-bit register while the contents of the second n-bit register are output and even serial data words are stored within the second n-bit register while the contents of the first n-bit register are output. By alternating data storage and data presentation the problem with setup time observed in prior art is eliminated.